Table of Contents
Advertisement
In the case of successive read and write cycles, such as in burst transfer or block transfer, a refresh
or external bus released state may be inserted after a write cycle. Since the DTC has a lower
priority than the DMAC, the DTC does not operate until the DMAC releases the bus.
When DMA cycle reads or writes are accesses to on-chip memory or internal I/O registers, these
DMA cycles can be executed at the same time as refresh cycles or external bus release. However,
simultaneous operation may not be possible when a write buffer is used.
7.4.12
NMI Interrupts and DMAC
When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An
NMI interrupt does not affect the operation of the DMAC in other modes.
In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit
are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
If the DTME bit is cleared during burst mode transfer, the DMAC discontinues transfer on
completion of the 1-byte or 1-word transfer in progress, then releases the bus, which passes to the
CPU.
The channel on which transfer was interrupted can be restarted by setting the DTME bit to 1 again.
Figure 7.23 shows the procedure for continuing transfer when it has been interrupted by an NMI
interrupt on a channel designated for burst mode transfer.
Resumption of
transfer on interrupted
channel
DTE= 1
DTME= 0
Set DTME bit to 1
Transfer continues
Figure 7.23 Example of Procedure for Continuing Transfer on Channel Interrupted by
Rev. 3.0, 10/02, page 188 of 686
[1]
No
Yes
[2]
NMI Interrupt
[1]
Check that DTE = 1 and
DTME = 0 in DMABCRL.
[2]
Write 1 to the DTME bit.
Transfer ends
Advertisement
Table of Contents
