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12.3
Operation
12.3.1
Watchdog Timer Mode
To use the WDT as a watchdog timer, set the WT/IT bit in TCSR and the TME bit to 1.
TCNT does not overflow while the system is operating normally. Software must prevent TCNT
overflows by rewriting the TCNT value (normally be writing H'00) before overflows occurs.
When the RSTE bit of the RSTCSR is set to 1, and if the TCNT overflows, an internal reset signal
for this LSI is issued. In this case, select power-on reset or manual reset by setting the RSTS bit of
the RSTCSR to 0.
If a reset caused by a signal input to the RES pin occurs at the same time as a reset caused by a
WDT overflow, the RES pin reset has priority and the WOVF bit in RSTCSR is cleared to 0. The
internal reset signal is output for 518 states.
When the TCNT overflows in watchdog timer mode, the WOVF bit of the RSTCSR is set to 1. If
the RSTE bit of the RSTCSR has been set to 1, an internal reset signal for the entire LSI is
generated at TCNT overflow.
H'FF
H'00
Internal reset signal*
WT/
: Timer mode select bit
TME
: Timer enable bit
Note: * With WDT0, the internal reset signal is generated only when the RSTE bit is set to 1.
TCNT value
WT/
= 1
H'00 written
TME = 1
to TCNT
Figure 12.2 Operation in Watchdog Timer Mode
Overflow
WOVF = 1
WT/
= 1
TME = 1
Internal reset
generated
518 states (WDT0)
Rev. 3.0, 10/02, page 351 of 686
Time
H'00 written
to TCNT
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