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2.4.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is two bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)
2.4.3
Extended Control Register (EXR)
EXR is an 8-bit register that manipulates the LDC, STC, ANDC, ORC, and XORC instructions.
When these instructions except for the STC instruction is executed, all interrupts including NMI
will be masked for three states after execution is completed.
Bit
Bit Name
7
T
6 to
–
3
2 to 0 I2
I1
I0
SP (ER7)
Figure 2.8 Stack
Initial Value R/W
0
R/W
1
–
1
R/W
Description
Trace Bit
When this bit is set to 1, a trace exception is
generated each time an instruction is executed. When
this bit is cleared to 0, instructions are executed in
sequence.
Reserved
These bits are always read as 1.
These bits designate the interrupt mask level (0 to 7).
For details, refer to section 5, Interrupt Controller.
Free area
Stack area
Rev. 3.0, 10/02, page 29 of 686
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