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7.4.3
Idle Mode
Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one
byte or word is transferred in response to a single transfer request, and this is executed the number
of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The
transfer direction can be specified by the DTDIR bit in DMACR. Table 7.4 summarizes register
functions in idle mode.
Table 7.4
Register Functions in Idle Mode
Register
23
MAR
23
15
H'FF
IOAR
15
ETCR
MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is
neither incremented nor decremented each time a byte or word is transferred. IOAR specifies the
lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7.5
illustrates operation in idle mode.
MAR
The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a
transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If
the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC. The maximum
number of transfers, when H'0000 is set in ETCR, is 65,536.
Transfer requests (activation sources) consist of A/D conversion end interrupt, SCI transmission
complete and reception complete interrupts, and TPU channel 0 to 2 compare match/input capture
Function
DTDIR = 0
DTDIR = 1
0
Source
Destination
address
address
register
register
0
Destination
Source
address
address
register
register
0
Transfer counter
Figure 7.5 Operation in Idle Mode
Initial Setting
Start address of
transfer destination
or transfer source
Start address of
transfer source or
transfer destination
Number of transfers Decremented every
Transfer
1 byte or word transfer performed in
response to 1 transfer request
Rev. 3.0, 10/02, page 167 of 686
Operation
Fixed
Fixed
transfer, transfer
ends when cunt
reaches H'0000
IOAR
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