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5.4
Interrupt Sources
5.4.1
External Interrupts
There are eight external interrupts: NMI, IRQ7, and IRQ5 to IRQ0. These interrupts can be used to
restore this LSI from software standby mode. IRQ6 is an interrupt only for the on-chip USB.
However, IRQ6 is functionally same as IRQ7 restore this LSI from software standby mode. IRQ6
is functionally same as IRQ7 and IRQ5 to IRQ0.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function. Since interrupt request
flags IRQ7F to IRQ0F are set when the setting condition is satisfied, regardless of the IER setting,
only the necessary flags should be referenced.
A block diagram of interrupts IRQ7 to IRQ0 is shown in figure 5.2.
input
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0
IRQnSCA, IRQnSCB
Edge / level
detection curcuit
Clear signal
IRQnE
IRQnF
S
Q
R
Rev. 3.0, 10/02, page 83 of 686
IRQn interrupt
request
Note: n = 7 to 0
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