Usage Notes; Contention Between Interrupt Generation And Disabling; Table 5.6 Interrupt Source Selection And Clearing Control - Hitachi H8S/2215 Series Hardware Manual

Table 5.6 Interrupt Source Selection and Clearing Control
Settings
DMAC DTC
DTA DTCE
0 0
1
1 *
Legend:
Ο: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
∆: The relevant interrupt is used. The interrupt source is not cleared.
X: The relevant bit cannot be used.
Notes on Use: The SCI interrupt source is cleared when the DMAC or DTC reads or writes to the
prescribed register, and is not dependent upon the DTA bit, DTCE bit, or DISEL bit.
5.7

Usage Notes

5.7.1

Contention between Interrupt Generation and Disabling

When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored.
The same also applies when an interrupt source flag is cleared to 0.
Figure 5.7 shows an example in which the TGIEA bit in the TPU's TIER_0 is cleared to 0.
The above contention will not occur if an enable bit or interrupt source flag is cleared to 0 while
the interrupt is masked.
Interrupt Sources Selection/Clearing Control
DISEL DMAC
∆
*
∆
0
∆
1
Ο
*
DTC CPU
Ο
X
Ο
X
∆ Ο
X X
*: Don't care
Rev. 3.0, 10/02, page 95 of 686