Phase Counting Mode; Figure 10.24 Example Of Pwm Mode Operation (3) - Hitachi H8S/2215 Series Hardware Manual

TCNT value
TGRB rewritten
TGRA
TGRB
H'0000
TIOCA
TCNT value
TGRB rewritten
TGRA
TGRB
H'0000
TIOCA
TCNT value
TGRB rewritten
TGRA
TGRB
H'0000
TIOCA
10.5.5

Phase Counting Mode

In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1 and 2. When
phase counting mode is set, an external clock is selected as the counter input clock and TCNT
operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1
and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of TIOR,
TIER, and TGR are valid, and input capture/compare match and interrupt functions can be used.
This can be used for two-phase encoder pulse input. When overflow occurs while TCNT is
Output does not change when cycle register and duty register
compare matches occur simultaneously
TGRB rewritten
Output does not change when cycle register and duty
register compare matches occur simultaneously
TGRB rewritten

Figure 10.24 Example of PWM Mode Operation (3)

TGRB rewritten
0% duty
TGRB rewritten
100% duty
100% duty
TGRB
rewritten
TGRB rewritten
0% duty
Rev. 3.0, 10/02, page 305 of 686
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