Figure 13.19 Sample Sci Transmission Operation In Clocked Synchronous Mode - Hitachi H8S/2215 Series Hardware Manual

4. The SCI checks the TDRE flag at the timing for sending the MSB (bit 7).
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TDRE flag maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt request
is generated. The SCK pin is fixed high.
Figure 13.20 shows a sample flow chart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure that the receive error flags are cleared to 0 before starting transmission. Note that
clearing the RE bit to 0 does not clear the receive error flags.
Synchronization
clock
Serial data
TDRE
TEND
TXI interrupt
request generated

Figure 13.19 Sample SCI Transmission Operation in Clocked Synchronous Mode

Transfer direction
Bit 0 Bit 1
Data written to TDR
and TDRE flag cleared
to 0 in TXI interrupt
service routine
1 frame
Bit 7 Bit 0 Bit 1
TXI interrupt
request generated
Rev. 3.0, 10/02, page 399 of 686
Bit 6 Bit 7
TEI interrupt request
generated