Reset Exception Handling; Figure 4.1 Reset Sequence (Modes 2 And 3: Not Available In This Lsi) - Hitachi H8S/2215 Series Hardware Manual

4.3.2

Reset Exception Handling

When the RES or MRES pin goes high after being held low for the necessary time, this LSI starts
reset exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are initialized,
the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.1 and 4.2 show examples of the reset sequence.
φ
,
Address bus
,
D15 to D0
(1) : Reset exception handling vector address (for a power-on reset, (1) = H'000000
for a manual reset, (1) = H'000002)
(2) : Start address (contents of reset exceptiion handling vector address)
(3) : Start address ((3) = (2))
(4) : First program instruction

Figure 4.1 Reset Sequence (Modes 2 and 3: Not available in this LSI)

Rev. 3.0, 10/02, page 68 of 686
Vector Internal Prefetch of first program
fetch processing instruction
(1)
High
(2)
(3)
(4)