Figure 7.1 Block Diagram Of Dmac - Hitachi H8S/2215 Series Hardware Manual

A block diagram of the DMAC is shown in figure 7.1.
Internal interrupts
TGI0A
TGI1A
TGI2A
TXI0
RXI0
TXI1
RXI1
ADI
USB request signals
Interrupt signals
DEND0A
DEND0B
DEND1A
DEND1B
Legend
: DMA write enable register
DMAWER
: DMA terminal control register *
DMATCR
: DMA band control register (for all channels)
DMABCR
DMACR : DMA control register
MAR : Memory address register
IOAR : I/O address register
: Executive transfer counter register
ETCR
Note: * Reserved register
Rev. 3.0, 10/02, page 142 of 686
Internal address bus
Control logic
DMAWER
DMATCR
DMACR0A
DMACR0B
DMACR1A
DMACR1B
DMABCR
Data buffer
Internal address bus

Figure 7.1 Block Diagram of DMAC

Addres buffer
Processor
MAR0A
IOAR0A
ETCR0A
MAR0B
IOAR0B
ETCR0B
MAR1A
IOAR1A
ETCR1A
MAR1B
IOAR1B
ETCR1B