Hitachi H8S/2215 Series Hardware Manual page 430

Bit Bit Name Initial Value
2 ACS2 0
1 ACS1 0
0 ACS0 0
Note: * Cannot be used in this LSI because the operating frequency ø in this LSI is 13 MHz or
greater.
Rev. 3.0, 10/02, page 372 of 686
R/W Description
R/W Asynchronous Clock Source Select 2 to 0
R/W These bits select the clock source in asynchronous
mode. When an average transfer rate is selected, the
R/W
base clock is set automatically regardless of the ABCS
value. Note that average transfer rates are not supported
for operating frequencies other than 10.667 MHz and 16
MHz. The setting in bits ACS2 to ACS0 is valid when
external clock input is used (CKE1 = 1 in SCR) in
asynchronous mode (C/A = 0 in SMR).
000: External clock input
001: 115.152 kbps average transfer rate (for ø =
10.667 MHz only) is selected* (SCI_0 operates
on base clock with frequency of 16 times
transfer rate)
010: 460.606 kbps average transfer rate (for ø =
10.667 MHz only) is selected* (SCI_0 operates
on base clock with frequency of 8 times transfer
rate)
011: Reserved
100: TPU clock input (AND of TIOCA1 and TIOCA2)
The signal generated by TIOCA1 and TIOCA2,
which are the compare match outputs for TPU_1
and TPU_2 or PWM outputs, is used as a base
clock. Note that IRQ0 and IRQ1 cannot be used
since TIOCA1 and TIOCA2 are used as outputs.
The high pulse width for TIOCA1 should be its
low pulse width or less.
101: 115.196 kbps average transfer rate (for ø = 16
MHz only) is selected (SCI_0 operates on base
clock with frequency of 16 times transfer rate)
110: 460.784 kbps average transfer rate (for ø = 16
MHz only) is selected (SCI_0 operates on base
clock with frequency of 16 times transfer rate)
111: 720 kbps average transfer rate (for ø = 16 MHz
only) is selected (SCI_0 operates on base clock
with frequency of 8 times transfer rate)