Port 3 Register (Port3); Port 3 Open-Drain Control Register (P3Odr) - Hitachi H8S/2215 Series Hardware Manual

9.2.3

Port 3 Register (PORT3)

PORT3 shows the pin states. It cannot be written to. Writing of output data for the port 3 pins (P36
to P30) must always be performed on P3DR.
Bit Bit Name Initial Value
−
7 Undefined
−
6 P36 *
−
5 P35
*
−
4 P34 *
−
3 P33
*
−
2 P32
*
−
1 P31
*
−
0 P30
*
Note: * Determined by the state of pins P36 to P30.
9.2.4

Port 3 Open-Drain Control Register (P3ODR)

P3ODR controls the PMOS on/off status for each port 3 pin (P36 to P30).
Bit Bit Name Initial Value
−
7 Undefined
6 P36ODR 0
5 P35ODR 0
4 P34ODR 0
3 P33ODR 0
2 P32ODR 0
1 P31ODR 0
0 P30ODR 0
Rev. 3.0, 10/02, page 226 of 686
R/W Description
−
Reserved
This bit is undefined and cannot be modified.
R If a port 3 read is performed while P3DDR bits are set to
1, the P3DR values are read. If a port 3 read is performed
R
while P3DDR bits are cleared to 0, the pin states are read.
R
R
R
R
R
R/W Description
−
Reserved
This bit is undefined and cannot be modified.
R/W Setting a P3ODR bit to 1 makes the corresponding port 3
pin an NMOS open-drain output pin, while clearing the bit
R/W
to 0 makes the pin a CMOS output pin.
R/W
R/W
R/W
R/W
R/W