Timing Of On-Chip Supporting Modules; Table 24.7 Timing Of On-Chip Supporting Modules - Hitachi H8S/2215 Series Hardware Manual

24.4.4

Timing of On-Chip Supporting Modules

Table 24.7 lists the timing of on-chip supporting modules.

Table 24.7 Timing of On-Chip Supporting Modules

Conditions: V = PLL V
CC
Dr V =AV
SS
T = –20°C to +75°C (regular specifications), T
a
specifications)
Item
I/O port Output data delay
time
Input data setup time t
Input data hold time
TPU Timer output delay
time
Timer input setup
time
Timer clock input
setup time
Timer
clock
pulse
width
TMR Timer output delay
time
Timer reset input
setup time
Timer clock input
setup time
Timer
clock
pulse
width
Rev. 3.0, 10/02, page 664 of 686
=Dr V =2.7 V to 3.6 V, Vref=2.7 V to AV
CC CC
= 0 V, φ =13 MHz to 16 MHz,
SS
Symbol
t
PWD
PRS
t
PRH
t
TOCD
t
TICS
t
TCKS
Single t
TCKWH
edge
Both t
TCKWL
edges
t
TMOD
T
TMRS
t
TMCS
Single t
TMCWH
edge
Both T
TMCWL
edges
= –40°C to +85°C (wide-range
a
Min Max
— 60
50 —
50 —
— 60
40 —
40 —
1.5 —
2.5 —
— 60
50 —
50 —
1.5 —
2.5 —
, V = PLLAV
CC SS SS
Unit Test Conditions
ns Figure 24.12
ns Figure 24.13
ns Figure 24.14
t
cyc
ns Figure 24.15
ns Figure 24.17
ns Figure 24.16
t
cyc
=