Dtc Transfer Count Register B (Crb); Dtc Enable Registers (Dtcera To Dtcerf) - Hitachi H8S/2215 Series Hardware Manual

bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is transferred, and the
contents of CRAH are sent when the count reaches H'00. This operation is repeated.
8.2.6

DTC Transfer Count Register B (CRB)

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
8.2.7

DTC Enable Registers (DTCERA to DTCERF)

DTCER which is comprised of seven registers, DTCERA to DTCERG, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 8.1. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set
at one time (only at the initial setting) by writing data after executing a dummy read on the
relevant register.
Bit Bit Name Initial Value
7 DTCEn7 0
6 DTCEn6 0
5 DTCEn5 0
4 DTCEn4 0
3 DTCEn3 0
2 DTCEn2 0
1 DTCEn1 0
0 DTCEn0 0
R/W Description
R/W DTC Activation Enable 7 to 0
R/W
Setting these bits to 1 specifies a relevant interrupt source
R/W
to a DTC activation source.
R/W
[Clearing conditions]
R/W
•
R/W
When the DISEL bit is 1 and the data transfer has
R/W
ended
R/W
•
When the specified number of transfers have ended
These bits are not cleared when the DISEL bit is 0 and
the specified number of transfers have not ended
Rev. 3.0, 10/02, page 199 of 686