Figure 10.17 Input Capture Buffer Operation; Figure 10.18 Example Of Buffer Operation Setting Procedure - Hitachi H8S/2215 Series Hardware Manual

• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register. This operation is
illustrated in figure 10.17.
Input capture
signal
Buffer register
Example of Buffer Operation Setting Procedure: Figure 10.18 shows an example of the buffer
operation setting procedure.
Buffer operation
Select TGR function
Set buffer operation
<Buffer operation>

Figure 10.18 Example of Buffer Operation Setting Procedure

Examples of Buffer Operation
1. When TGR is an output compare register
Figure 10.19 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in
this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B. As buffer operation has been set, when compare match A occurs
the output changes and the value in buffer register TGRC is simultaneously transferred to timer
general register TGRA. This operation is repeated each time compare match A occurs. For
details of PWM modes, see section 10.5.4, PWM Modes.
Rev. 3.0, 10/02, page 300 of 686
Timer general

Figure 10.17 Input Capture Buffer Operation

[1]
[2]
[3]
Start count
register
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
[2]
Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
[3] Set the CST bit in TSTR to 1 start the count
operation.
TCNT