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φ
Address bus
(area A)
(area B)
Data bus
(a) Idle cycle not inserted
(ICIS0 = 0)
(3) Relationship between Chip Select (CS
Depending on the system's load conditions, the RD signal may lag behind the CS signal. An
example is shown in figure 6.24.
In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap
between the bus cycle A RD signal and the bus cycle B CS signal.
Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and
CS signals.
In the initial state after reset release, idle cycle insertion (b) is set.
φ
Address bus
(area A)
(area B)
Possibility of overlap between
Figure 6.24 Relationship between Chip Select (CS
Rev. 3.0, 10/02, page 134 of 686
Bus cycle A
Bus cycle B
T
T
T
T
T
1
2
3
1
2
Long output floating time
Figure 6.23 Example of Idle Cycle Operation (2)
CS) Signal and Read (RD
CS
CS
Bus cycle A
Bus cycle B
T
T
T
T
T
1
2
3
1
2
(area B) and
(a) Idle cycle not inserted
(ICIS1 = 0)
Bus cycle A
T
1
Address bus
(area A)
(area B)
Data bus
Data collision
(b) Idle cycle inserted
RD) Signal
RD
RD
Bus cycle A
T
1
φ
Address bus
(area A)
(area B)
(b) Idle cycle inserted
CS) and Read (RD
CS
CS
Bus cycle B
T
T
T
T
T
2
3
I
1
2
(Initial value ICIS0 = 1)
Bus cycle B
T
T
T
T
T
2
3
I
1
2
(Initial value ICIS1 = 1)
RD)
RD
RD
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