Hitachi H8S/2215 Series Hardware Manual page 427

Bit Bit Name Initial Value
2 TEND 1
1 MPB 0
0 MPBT 0
R/W Description
R Transmit End
[Setting conditions]
· When the TE bit in SCR is 0
· When TDRE = 1 at transmission of the last bit of a 1-
byte serial transmit character
[Clearing conditions]
· When 0 is written to TDRE after reading TDRE = 1
· When the DTC is activated by a TXI interrupt and
writes data to TDR
R Multiprocessor Bit
MPB stores the multiprocessor bit in the receive data.
When the RE bit in SCR is cleared to 0 its previous state
is retained. This bit retains its previous state when the
RE bit in SCR is cleared to 0.
R/W Multiprocessor Bit Transfer
MPBT stores the multiprocessor bit to be added to the
transmit data.
Rev. 3.0, 10/02, page 369 of 686