Isochronous-Out Transfer (Dual-Fifo) (When Ep3O Is Specified As Endpoint) - Hitachi H8S/2215 Series Hardware Manual

Hitachi single-chip microcomputer
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15.5.9
Isochronous–Out Transfer (Dual-FIFO) (When EP3o is Specified as Endpoint)
EP3o has two 128-byte (maximum) FIFOs, however the user can perform data transmission and
transmit data writes without being aware of this dual-FIFO configuration.
In isochronous transfer, as a transmission is performed once a frame (1ms), the hardware
automatically switches FIFOs when the hardware receives the SOF. (Even when SOF cannot be
received by an error, enabling the SOF marker function allows the hardware to automatically
switch the FIFOs every 1ms.)
Two FIFOs are switched when the SOF is received, the FIFO used to transfer data from the host to
the firmware differs from the FIFO from which the firmware reads transmit data. Accordingly, no
contention occurs between one FIFO read and the other FIFO write. The firmware read the data in
the previous frame. As two FIFOs are automatically switched when the SOF is received, data must
be read within a single frame.
The USB function receives data from the host after an OUT token has been received. If a data
error occurs on data reception, the USB function sets the TF flag to 1; if no data error occurs, the
USB function sets the TS flag to 1.
The firmware first calls the isochronous transfer process routine via the SOF interrupt, checks the
time stamp, and then reads from the FIFO. Accordingly, the firmware checks whether a data error
occurs or not via status information indicated by the TF and TS flags. These TF and TS flags
indicate the status of the FIFO currently being read.
Rev. 3.0, 10/02, page 506 of 686

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