Hitachi H8S/2215 Series Hardware Manual page 213

Bit Bit Name Initial Value R/W
7 DTE1B 0
6 DTE1A 0
5 DTE0B 0
4 DTE0A 0
3 DTIE1B 0
2 DTIE1A 0
1 DTIE0B 0
0 DTIE0A 0
Description
R/W Data Transfer Enable:
R/W When DTE = 0, data transfer is disabled and the activation
source selected by the data transfer factor setting is ignored.
R/W
If the activation source is an internal interrupt, an interrupt
R/W
request is issued to the CPU or DTC. If the DTIE bit is set to
1when DTE = 0, the DMAC regards this as indicating the end
of a transfer, and issues a transfer end interrupt request to
the CPU or DTC.
The conditions for the DTE bit being cleared to 0 are as
follows:
•
When initialization is performed
•
When the specified number of transfers have been
completed in a transfer mode other than repeat mode
•
When 0 is written to the DTE bit to forcibly abort the
transfer, or for a similar reason
When DTE = 1, data transfer is enabled and the DMAC waits
for a request by the activation source selected by the data
transfer factor setting. When a request is issued by the
activation source, DMA transfer is executed. The condition for
the DTE bit being set to 1 is as follows:
•
When 1 is written to the DTE bit after the DTE bit is read
as 0
0: Data transfer disabled
1: Data transfer enabled
R/W Data Transfer End Interrupt Enable:
R/W These bits enable or disable an interrupt to the CPU or DTC
when transfer ends. If the DTIE bit is set to 1 when DTE = 0,
R/W
the DMAC regards this as indicating the end of a transfer,
R/W
and issues a transfer end interrupt request to the CPU or
DTC.
A transfer end interrupt can be canceled either by clearing
the DTIE bit to 0 in the interrupt handling routine, or by
performing processing to continue transfer by setting the
transfer counter and address register again, and then setting
the DTE bit to 1.
0: Transfer end interrupt disabled
1: Transfer end interrupt enabled
Rev. 3.0, 10/02, page 155 of 686