Register Configuration; Table7.1 Short Address Mode And Full Address Mode (For 1 Channel: Example Of Channel 0) - Hitachi H8S/2215 Series Hardware Manual

7.2

Register Configuration

The DMAC registers are listed below. The DMAC register functions differs depending on the
address modes: short address mode and full address mode. The DMAC register functions are
described in each address mode. Short address mode or full address mode can be selected for
channels 1 and 0 independently by means of bits FAE1 and FAE0.
Table7.1 Short Address Mode and Full Address Mode (For 1 Channel: Example of
Channel 0)
FAE0 Description
0
Short address mode specified (channels A and B operate independently)
1
Full address mode specified (channels A and B operate combination)
• Memory address register 0A (MAR0A)
• I/O address register 0A (IOAR0A)
• Transfer count register 0A (ETCR0A)
• Memory address register 0B (MAR0B)
• I/O address register 0B (IOAR0B)
• Transfer count register 0B (ETCR0B)
Specifies transfer source/transfer destination address
MAR0A
IOAR0A Specifies transfer destination/transfer source address
Specifies number of transfers
ETCR0A
Specifies transfer size, mode, activation source, etc.
DMACR0A
Specifies transfer source/transfer destination address
MAR0B
Specifies transfer destination/transfer source address
IOAR0B
Specifies number of transfers
ETCR0B
Specifies transfer size, mode, activation source, etc.
DMACR0B
Specifies transfer source address
MAR0A
Specifies transfer destination address
MAR0B
Not used
IOAR0A
Not used
IOAR0B
Specifies number of transfers
ETCR0A
Specifies number of transfers (used in block transfer mode only)
ETCR0B
Specifies transfer size, mode, activation source, etc.
DMACR0A
DMACR0B
Rev. 3.0, 10/02, page 143 of 686