Figure 24.7 Basic Bus Timing (Two-State Access) - Hitachi H8S/2215 Series Hardware Manual

ø
t
AD
A23 to A0
t
CSD
to
(read)
D15 to D0
(read)
,
(write)
D15 to D0
(write)

Figure 24.7 Basic Bus Timing (Two-State Access)

T1 T2
t
AS
t t
ASD ASD
t t
RSD1 ACC2
t
AS
t
ACC3
t t
WRD2
t
AS
t
WSW1
t
WDD
t
AH
t
RSD2
t t
RDS RDH
WRD2
t
AH
t
WDH
Rev. 3.0, 10/02, page 659 of 686