Port F Data Direction Register (Pfddr); Port F Data Register (Pfdr) - Hitachi H8S/2215 Series Hardware Manual

9.11.1

Port F Data Direction Register (PFDDR)

The individual bits of PFDDR specify input or output for the pins of port F.
Bit Bit Name Initial Value
7 PF7DDR 1/0*
6 PF6DDR 0
5 PF5DDR 0
4 PF4DDR 0
3 PF3DDR 0
2 PF2DDR 0
1 PF1DDR 0
0 PF0DDR 0
Note: * In modes 4 to 6, set to 1; in mode 7 cleared to 0.
9.11.2

Port F Data Register (PFDR)

PFDR stores output data for the port F pins.
Bit Bit Name Initial Value
7 PF7DR 0
6 PF6DR 0
5 PF5DR 0
4 PF4DR 0
3 PF3DR 0
2 PF2DR 0
1 PF1DR 0
0 PF0DR 0
Rev. 3.0, 10/02, page 256 of 686
R/W Description
W Modes 4 to 6:
Pin PF7 functions as the φ output pin when the
W
corresponding PFDDR bit is set to 1, and as an input port
W
when the bit is cleared to 0. The input/output direction
specification in PFDDR is ignored for pins PF6 to PF3,
W
which are automatically designated as bus control
W
outputs. Pins PF2 to PF0 are made bus control
W
input/output pins by bus controller settings. Otherwise,
setting a PFDDR bit to 1 makes the corresponding pin an
W
output port, while clearing the bit to 0 makes the pin an
W
input port.
Mode 7:
Setting a PFDDR bit to 1 makes the corresponding port F
pin PF6 to PF0 an output port, or in the case of pin PF7,
the φ output pin. Clearing the bit to 0 makes the pin an
input port.
R/W Description
R/W An output data for a pin is stored when the pin function is
specified to a general purpose output port.
R/W
R/W
R/W
R/W
R/W
R/W
R/W