ø
Address
Write signal
Input sampling
timing
ADF
Legend
(1)
(2)
t
D
t
SPL
t
CONV
Table 16.3 A/D Conversion Time (Single Mode)
Item
A/D conversion start
delay
Input sampling time t
A/D conversion time t
Note: All values represent the number of states.
Table 16.4 A/D Conversion Time (Scan Mode)
CKS1
CKS0
0
0
1
1
0
1
(1)
(2)
t
D
: ADCSR write cycle
: ADCSR address
: A/D conversion start delay
: Input sampling time
: A/D conversion time
Figure 16.5 A/D Conversion Timing
Symbol
CKS1 = 0
CKS0 = 0
Min Typ Max Min Typ Max Min Typ Max Min Typ Max
t
18
—
D
—
127 —
SPL
515 —
CONV
Conversion Time (State)
512 (Fixed)
256 (Fixed)
128 (Fixed)
64 (Fixed)
t
SPL
t
CONV
CKS0 = 1
33
10
—
17
—
63
—
530 259 —
266 131 —
CKS1 = 1
CKS0 = 0
CKS0 = 1
6
—
9
4
—
31
—
—
134 67
Rev. 3.0, 10/02, page 543 of 686
—
5
15
—
—
68