Figure 7.20 Example Of Dreq Level Activated Normal Mode Transfer - Hitachi H8S/2215 Series Hardware Manual

DREQ DREQ Pin Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ
DREQ DREQ
pin is selected to 1.
Figure 7.20 shows an example of DREQ level activated normal mode transfer.
f
DREQ
Address bus
DMA control
Idle
Channel
[1] Acceptance after transfer enabling; the
edge of f, and the request is held.
[2] [5] The request is cleared at the next bus break, and activation is started in the DMAC.
[3] [6] Start of DMA cycle.
[4] [7] Acceptance is resumed after the write cycle is completed.
(As in [1], the
is held.)
Figure 7.20 Example of DREQ
DREQ signal sampling is performed every cycle, with the rising edge of the next φ cycle after the
end of the DMABCR write cycle for setting the transfer enabled state as the starting point.
When the DREQ signal low level is sampled while acceptance by means of the DREQ signal is
possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the
request is cleared. Acceptance resumes after the end of the write cycle, DREQ pin low level
sampling is performed again, and this operation is repeated until the transfer ends.
Note : The DREQ signal of this chip is an internal signal of chip, so it is not output from the pin.
Figure 7.21 shows an example of DREQ level activated block transfer mode transfer.
DMA
Bus release
read
Transfer
source
Read Write
Request clear period
Request
Minimum of 2 cycles
[1] [2] [3]
signal low level is sampled on the rising edge of f, and the request
DREQ Level Activated Normal Mode Transfer DREQ DREQ
DMA Bus
write release
Transfer
destination
Idle Read
Request clear period
Request
Minimum of 2 cycles
[4] [5] [6]
Acceptance resumes
signal low level is sampled on the rising
DMA DMA Bus
read write release
Transfer Transfer
source destination
Write Idle
[7]
Acceptance resumes
Rev. 3.0, 10/02, page 185 of 686