Port G; Port G Data Direction Register; Table 9.70 Pf0 Pin Function - Hitachi H8S/2215 Series Hardware Manual

Table 9.70 PF0 Pin Function

Operating Mode
BRLE
PF0DDR
Pin function
Notes: * When used as an external interrupt input pin, do not use as an I/O pin for another function.
9.12

Port G

Port G is a 5-bit I/O port that also has functioning as external interrupt input (IRQ7).and bus
control output (CS0 to CS3). The port G has the following registers.
• Port G data direction register (PGDDR)
• Port G data register (PGDR)
• Port G register (PORTG)
9.12.1 Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G. If port G is, an
undefined value will be read.
Bit Bit Name Initial Value
−
7 to Undefined
5
4 PG4DDR 0/1*
3 PG3DDR 0
2 PG2DDR 0
1 PG1DDR 0
0 PG0DDR 0
Note: * In modes 4 to 6, set to 1; in mode 7 cleared to 0.
Modes 4 to 6
0
0 1
PF0 input PF0 output
R/W Description
−
Reserved
These bits are undefined and cannot be modified.
W Modes 4 to 6:
Setting a PGDDR bit to 1 makes the PG4 to PG1 pins bus
W
control signal outputs, while clearing the bit to 0 makes
W
the pin input ports. signal outputs, while clearing the bit to
0 makes the pin input ports. Setting a PGDDR bit to 1
W
makes the PG0 pin an output port, while clearing the bit to
W
0 makes the pin an input port. PGDDR are ignored, and
port G pins automatically function as data.
Mode 7:
Setting a PGDDR bit to 1 makes the corresponding port G
pin an output port, while clearing the bit to 0 makes the
pin an input port.
−
1
−
0
BREQ input
PF0 input
IRQ2 input*
Rev. 3.0, 10/02, page 259 of 686
Mode 7
1
PF0 output