Section 12 Watchdog Timer; Features; Figure 12.1 Block Diagram Of Wdt - Hitachi H8S/2215 Series Hardware Manual

The watchdog timer (WDT) is an 8-bit timer that can generate an internal reset signal for this LSI
if a system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagram of the WDT is shown in figure 12.1.
12.1

Features

• Selectable from eight counter input clocks.
• Switchable between watchdog timer mode and interval timer mode
In watchdog timer mode
• If the counter overflows, it is possible to select whether this LSI is internally reset or not.
In interval timer mode
• If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
(interrupt request
Internal reset signal*
Legend
TCSR
TCNT
RSTCSR
Note: * The type of internal reset signal depends on a register setting.
WDT0104A_000020020100

Section 12 Watchdog Timer

Interrupt
WOVI
control
signal)
Reset
control
RSTCSR
: Timer control/status register
: Timer counter
: Reset control/status register

Figure 12.1 Block Diagram of WDT

Overflow
Clock
Clock
select
TCNT TSCR
Module bus
WDT
ø/2
ø/64
ø/128
ø/512
ø/2048
ø/8192
ø/32768
ø/131072
Internal clock
sources
Bus
interface
Rev. 3.0, 10/02, page 347 of 686