Chain Transfer; Figure 8.9 Chain Transfer Memory Map - Hitachi H8S/2215 Series Hardware Manual

8.5.4

Chain Transfer

Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 8.9 shows the memory map for chain transfer. When activated, the DTC reads the register
information start address stored at the vector address, and then reads the first register information
at that start address. After the data transfer, the CHNE bit will be tested. When it has been set to 1,
DTC reads next register information located in a consecutive area and performs the data transfer.
These sequences are repeated until the CHNE bit is cleared to 0.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Register information
DTC vector
address
Rev. 3.0, 10/02, page 210 of 686
start address

Figure 8.9 Chain Transfer Memory Map

Register information
CHNE=1
Register information
CHNE=0
Source
Destination
Source
Destination