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4.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace, trap instruction, or
interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur
simultaneously, they are accepted and processed in order of priority. Exception sources, the stack
structure, and operation of the CPU vary depending on the interrupt control mode. For details on
the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Exception Types and Priority
Priority
Exception Type
High
Reset
Trace
Interrupt
Low
Trap instruction
(TRAPA)
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.
Section 4 Exception Handling
Start of Exception Handling
Starts immediately after a low-to-high transition at the RES or
MRES pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low. The CPU enters the
manual reset state when the MRES pin is low.
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1. This is
enabled only in trace interrupt control mode 2. Trace exception
processing is not performed after RTE instruction execution.
Starts when execution of the current instruction or exception
handling ends, if an interrupt request has been issued. Note that
after executing the ANDC, ORC, XORC, or LDC instruction or at
the completion of reset exception processing, no interrupt is
detected.
Started by execution of a trap instruction (TRAPA). Trap exception
processing is always accepted in program execution state.
Rev. 3.0, 10/02, page 65 of 686
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