System Control Register (Syscr) - Hitachi H8S/2215 Series Hardware Manual

3.2.2

System Control Register (SYSCR)

SYSCR is used to select the interrupt control mode and the detected edge for NMI, select the
MRES input pin enable or disable, and enables or disables on-chip RAM.
Bit Bit Name
7 –
6 –
5 INTM1
4 INTM0
3 NMIEG
2 MRESE
1 –
0 RAME
Initial Value R/W
0 R/W
0 –
0 R/W
0 R/W
0 R/W
0 R/W
0 –
1 R/W
Description
Reserved
The write value should always be 0.
Reserved
These bits are always read as 0 and cannot be
modified.
These bits select the control mode of the interrupt
controller. For details of the interrupt control modes,
see section 5.6, Interrupt Control Modes and Interrupt
Operation.
00: Interrupt control mode 0
01: Setting prohibited
10: Interrupt control mode 2
11: Setting prohibited
NMI Edge Select
Selects the valid edge of the NMI interrupt input.
0: An interrupt is requested at the falling edge of NMI
input
1: An interrupt is requested at the rising edge of NMI
input
Manual reset Select
Enables or disables the MRES pin input.
0: The MRES pin input (manual reset) is disabled
1: The MRES pin input (manual reset) is enabled
The MRES input pin can be used.
Reserved
These bits are always read as 0 and cannot be
modified.
RAM Enable
Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
Rev. 3.0, 10/02, page 57 of 686