Table of Contents
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2.9
Usage Notes.......................................................................................................................53
2.9.1
Note on TAS Instruction Usage ...........................................................................53
2.9.2
STM/LTM Instruction Usage...............................................................................53
2.9.3
Note on Bit Manipulation Instructions .................................................................54
Section 3 MCU Operating Modes......................................................................55
3.1
Operating Mode Selection.................................................................................................55
3.2
Register Descriptions ........................................................................................................56
3.2.1
Mode Control Register (MDCR)..........................................................................56
3.2.2
System Control Register (SYSCR) ......................................................................57
3.3
Operating Mode Descriptions............................................................................................58
3.3.1
Mode 4 .................................................................................................................58
3.3.2
Mode 5 .................................................................................................................58
3.3.3
Mode 6 .................................................................................................................59
3.3.4
Mode 7 .................................................................................................................59
3.3.5
Pin Functions........................................................................................................59
3.4
Memory Map in Each Operating Mode.............................................................................61
Section 4 Exception Handling.............................................................................65
4.1
Exception Handling Types and Priority ............................................................................65
4.2
Exception Sources and Exception Vector Table ...............................................................65
4.3
Reset ..................................................................................................................................67
4.3.1
Reset Types ..........................................................................................................67
4.3.2
Reset Exception Handling ....................................................................................68
4.3.3
Interrupts after Reset ............................................................................................69
4.3.4
State of On-Chip Peripheral Modules after Reset Release ...................................69
4.4
Traces ................................................................................................................................70
4.5
Interrupts ...........................................................................................................................70
4.6
Trap Instruction .................................................................................................................71
4.7
Stack Status after Exception Handling ..............................................................................72
4.8
Notes on Use of the Stack .................................................................................................73
Section 5 Interrupt Controller ............................................................................75
5.1
Features .............................................................................................................................75
5.2
Input/Output Pins ..............................................................................................................77
5.3
Register Descriptions ........................................................................................................77
5.3.1
(IPRA to IPRG, IPRI to IPRK, IPRM).................................................................78
5.3.2
IRQ Enable Register (IER)...................................................................................79
5.3.3
IRQ Sense Control Registers H and L (ISCRH, ISCRL) .....................................80
5.3.4
IRQ Status Register (ISR) ....................................................................................82
5.4
Interrupt Sources ...............................................................................................................83
5.4.1
External Interrupts................................................................................................83
Rev. 3.0, 10/02, page xxx of lviii
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