Port B Data Direction Register (Pbddr); Port B Data Register (Pbdr) - Hitachi H8S/2215 Series Hardware Manual

9.7.1

Port B Data Direction Register (PBDDR)

The individual bits of PBDDR specify input or output for the pins of port B.
Bit Bit Name Initial Value
7 PB7DDR 0
6 PB6DDR 0
5 PB5DDR 0
4 PB4DDR 0
3 PB3DDR 0
2 PB2DDR 0
1 PB1DDR 0
0 PB0DDR 0
9.7.2

Port B Data Register (PBDR)

PBDR stores output data for the port B pins.
Bit Bit Name Initial Value
7 PB7DR 0
6 PB6DR 0
5 PB5DR 0
4 PB4DR 0
3 PB3DR 0
2 PB2DR 0
1 PB1DR 0
0 PB0DR 0
Rev. 3.0, 10/02, page 238 of 686
R/W Description
W Mode 7:
Setting a PBDDR bit to 1 makes the corresponding port B
W
pin an output port, while clearing the bit to 0 makes the
W
pin an input port.
W
Modes 4, 5, and 6:
If address output is enabled by the setting of bits AE3 to
W
AE0 in PFCR, the corresponding port B pins are address
W
outputs. When address output is disabled, setting a
W
PBDDR bit to 1 makes the corresponding port B pin an
output port, while clearing the bit to 0 makes the pin an
W
input port.
R/W Description
R/W An output data for a pin is stored when the pin function is
specified to a general purpose output port.
R/W
R/W
R/W
R/W
R/W
R/W
R/W