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15.3.41 USB Test Register 0 (UTSTR0)
UTSTR0 controls internal or external transceiver output signals. Setting the PTSTE bit to 1
specifies transceiver output arbitrarily. Table 15.3 shows the relationship between UTSTR0
settings and pin outputs.
Bit
Bit Name
Initial Value R/W
7
PTSTE
0
6 to 4 —
0
3
SUSPEND
0
OE
2
1
1
FSE0
0
0
VPO
0
Description
R/W
Pin Test Enable
Enables the test control of the internal/external
transceiver output signals.
When FADSEL in UCTLR is 0, the test control for the
internal transceiver output pins (USD+ and USD-) and
USPND pin are enabled.
When FADSEL in UCTLR is 1, the test control for the
external transceiver output pins (P17/OE, P15/FSE0,
P13/VPO, and PA3/SUSPND) and USPND pin are
enabled.
R
Reserved
These bits are always read as 0 and cannot be
modified.
R/W
Internal/External Transceiver Output Signal
R/W
Setting Bits
R/W
SUSPEND: Specifies USPND and PA3/SUSPND pin.
OE: Specifies internal transceiver OE signal and
R/W
P17/OE pin.
FSE0: Specifies internal transceiver FSE0 signal and
P15/FSE0 pin.
VPO: Specifies internal transceiver VPO signal and
P13/VPO pin.
Rev. 3.0, 10/02, page 477 of 686
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