Figure 6.20 Example Of Burst Rom Access Timing (When Ast0 = Brsts1 = 1); Figure 6.21 Example Of Burst Rom Access Timing (When Ast0 = Brsts1 = 0) - Hitachi H8S/2215 Series Hardware Manual

Full access Burst access
T T T T T T T
1 2 3 1 2 1 2
φ
Only lower address changed
Address bus
Data bus
Read data Read data Read data

Figure 6.20 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1)

Full access Burst access
T T T T
1 2 1 1
φ
Address bus
Only lower address changed
Data bus
Read data Read data Read data

Figure 6.21 Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0)

Rev. 3.0, 10/02, page 131 of 686