Multiprocessor Serial Data Transmission; Figure 13.13 Example Of Communication Using Multiprocessor Format (Transmission Of Data H'aa To Receiving Station A) - Hitachi H8S/2215 Series Hardware Manual

Hitachi single-chip microcomputer
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differentiate between the ID transmission cycle and the data transmission cycle. If the
multiprocessor bit is 1, the cycle is an ID transmission cycle; if the multiprocessor bit is 0, the
cycle is a data transmission cycle. Figure 13.13 shows an example of inter-processor
communication using the multiprocessor format. The transmitting station first sends the ID code of
the receiving station with which it wants to perform serial communication as data with a 1
multiprocessor bit added. It then sends transmit data as data with a 0 multiprocessor bit added.
When data with a 1 multiprocessor bit is received, the receiving station compares that data with its
own ID. The station whose ID matches then receives the data sent next. Stations whose ID do not
match continue to skip data until data with a 1 multiprocessor bit is again received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and ORER to 1, are inhibited until data with a 1 multiprocessor bit is received. On
reception of a receive character with a 1 multiprocessor bit, the MPB bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is rendered invalid. All other bit
settings are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Transmitting
Receiving
Serial
data
Legend
MPB: Multiprocessor bit
Figure 13.13 Example of Communication Using Multiprocessor Format
13.5.1

Multiprocessor Serial Data Transmission

Figure 13.14 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
Rev. 3.0, 10/02, page 392 of 686
station
Receiving
station A
station B
(ID = 01)
(ID = 02)
H'01
(MPB = 1)
ID transmission cycle =
receiving station
specification
(Transmission of Data H'AA to Receiving Station A)
Serial transmission line
Receiving
station C
(ID = 03)
H'AA
(MPB = 0)
Data transmission cycle =
Data transmission to
receiving station specified by ID
Receiving
station D
(ID = 04)

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