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15.6.5
EP2iPKTE, EP4iPKTE, EP2oRDFN and EP4oRDFN Bits of UTRG
(1) EP2iPKTE and EP4iPKTE
When DMA transfer is performed on EP2i and EP4i transmit data, the USB module
automatically performs the same processing as writing 1 to EP2iPKTE and EP4iPKTE if one
data FIFO (64 bytes) becomes full. Accordingly, to transfer data of integral multiples of 64
bytes, the user need not write EP2iPKTE and EP4iPKTE to 1. To transfer data of less than 64
bytes, the user must write EP2iPKTE and EP4iPKTE to 1 using the DMA transfer end
interrupt of the on-chip DMAC. If the user writes 1 to EP2iPKTE and EP4iPKTE in cases
other than the case when data of less than 64 bytes is transferred, excess transfer occurs and
correct operation cannot be guaranteed.
Figure 15.24 shows an example for transmitting 150 bytes of data from EP2i to the host. In this
case, internal processing the same as writing 1 to EP2iPKTE is automatically performed twice.
This kind of internal processing is performed when the currently selected data FIFO becomes
full. Accordingly, this processing is automatically performed only when 64-byte data is sent.
This processing is not performed automatically when data less than 64 bytes is sent.
Rev. 3.0, 10/02, page 514 of 686
64 bytes
EP2iPKTE
(Automatically
performed)
Figure 15.24 EP2iPKTE Operation in UTRG0
64 bytes
22 bytes
EP2iPKTE
EP2iPKTE is
(Automatically
not performed
performed)
Execute by DMA transfer
end interrupt (user)
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