AVCC
Vref
10 bit D/A
AVSS
AN0
AN1
AN2
AN3
AN14
Sample and
hold circuit
AN15
Legend:
ADCR
: A/D control register
ADCSR : A/D control/status register
ADDRA : A/D data register A
ADDRB : A/D data register B
ADDRC : A/D data register C
ADDRD : A/D data register D
Rev. 3.0, 10/02, page 534 of 686
Module data bus
A
A
A
D
D
D
D
D
D
R
R
R
A
B
C
+
Comparator
Figure 16.1 Block Diagram of A/D Converter
A
A
A
D
D
D
D
C
C
R
S
R
D
R
Control circuit
Time conversion start trigger from TPU or 8 bit timer
Internal data bus
/2
/4
/8
/16
ADI interrupt signal