Usb Endpoint Stall Register 1 (Uestl1) - Hitachi H8S/2215 Series Hardware Manual

15.3.10 USB Endpoint Stall Register 1 (UESTL1)

UESTL1 is used to forcibly stall the endpoints for EP4 and EP5. In addition, UESTL1 can cancel
all endpoint stall states. While the bit is set to 1, the corresponding endpoint returns a stall
handshake to the host. For details, refer to section 15.5.11, Stall Operations.
Bit Bit Name Initial Value R/W
7 SCME 0
6 to 3 — 0
2 EP5iSTL 0
1 EP4oSTL 0
0 EP4iSTL 0
Rev. 3.0, 10/02, page 456 of 686
Description
R/W Stall Cancellation Mode Enable
Controls stall cancellation mode.
When this bit is set to 1, the EPnSTL bit, which has
been set once, is automatically cleared to 0 after
returning a handshake to the host. This bit is common
to all endpoints. The stall cancellation mode cannot be
specified for each endpoint.
When this bit is cleared to 0, the EPnSTL bit, which
has been set once, cannot be cleared automatically.
To cancel the stall state of the EPn, clear the EPnSTL
bit.
0: Disables stall cancellation mode for all endpoints
(EP0 to EP5).
1: Enables stall cancellation mode for all endpoints
(EP0 to EP5).
R Reserved
These bits are always read as 0 and cannot be
modified.
R/W EP5i stall
0: Cancels the EP5i stall state.
1: Places the EP5i stall state.
R/W EP4o stall
0: Cancels the EP4o stall state.
1: Places the EP4o stall state.
R/W EP4i stall
0: Cancels the EP4i stall state.
1: Places the EP4i stall state.