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22.4.2
Clearing Software Standby Mode
Software standby mode is cleared by an external interrupt (NMI pin, IRQ7 pin, or IRQ0 to IRQ5
pins), or by means of the RES pin, MRES pin, or STBY pin.
• Clearing with an interrupt
When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to
the entire chip, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ7 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ5
is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
• Clearing with the RES or MRES pin
When the RES or MRES pin is driven low, clock oscillation is started. At the same time as
clock oscillation starts, clocks are supplied to the entire chip. Note that the RES or MRES pin
must be held low until clock oscillation stabilizes. When the RES or MRES pin goes high, the
CPU begins reset exception handling.
• Clearing with the STBY pin
When the STBY pin is driven low, a transition is made to hardware standby mode.
22.4.3
Setting Oscillation Stabilization Time after Clearing Software Standby Mode
Bits STS2 to STS0 in SBYCR should be set as described below.
• Using a Crystal Oscillator:
Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization
time).
Table 22.3 shows the standby times for different operating frequencies and settings of bits
STS2 to STS0.
• Using an External Clock
Set bits STS2 to STS0 as any value. Usually, minimum value is recommended. A 16-state
standby time cannot be used in the F-ZTAT version; a standby time of 2,048 states or longer
should be used.
Rev. 3.0, 10/02, page 616 of 686
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