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13.2
Input/Output Pins
Table 13.1 shows the serial pins for each SCI channel.
Table 13.1 Pin Configuration
Channel
Pin Name*
0
SCK0
RxD0
TxD0
1
SCK1
RxD1
TxD1
2
SCK2
RxD2
TxD2
Note: * Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the channel
designation.
13.3
Register Descriptions
The SCI has the following registers for each channel.
• Receive Shift Register (RSR)
• Receive Data Register (RDR)
• Transmit Data Register (TDR)
• Transmit Shift Register (TSR)
• Serial Mode Register (SMR)
• Serial Control Register (SCR)
• Serial Status Register (SSR)
• Smart Card Mode Register (SCMR)
• Serial Extended Mode Register (SEMR) (only for channel 0)
• Bit Rate Register (BRR)
13.3.1
Receive Shift Register (RSR)
RSR is a shift register that is used to receive serial data input to the RxD pin and convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
I/O
Function
I/O
SCI_0 clock input/output
Input
SCI_0 receive data input
Output
SCI_0 transmit data output
I/O
SCI_1 clock input/output
Input
SCI_1 receive data input
Output
SCI_1 transmit data output
I/O
SCI_2 clock input/output
Input
SCI_2 receive data input
Output
SCI_2 transmit data output
Rev. 3.0, 10/02, page 361 of 686
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