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1.1
Overview
• High-speed H8S/2000 central processing unit with 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
65 basic instructions
• Various peripheral functions
DMA controller (DMAC)
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
Boundary scan
Universal serial bus (USB)
10-bit A/D converter
8-bit D/A converter
Clock pulse generator
• On-chip memory
ROM
Product Code
F-ZTAT Version
HD64F2215
HD64F2215U
Masked ROM
HD6432215A
Version
HD6432215B
HD6432215C
• General I/O ports
I/O pins:
Input-only pins:
• Supports various power-down states
• Compact package
Package
TQFP-120
P-LFBGA-112
Section 1 Overview
ROM
256 kbytes
256 kbytes
256 kbytes
128 kbytes
64 kbytes
Modes 4 and 5
41
15
(Code)
Body Size
14.0 × 14.0 mm
TFP-120
10.0 × 10.0 mm
BP-112
RAM
16 kbytes
16 kbytes
16 kbytes
16 kbytes
8 kbytes
Mode 6
Mode 7
41
68
23
7
Pin Pitch
0.4 mm
0.8 mm
Rev. 3.0, 10/02, page 1 of 686
Remarks
SCI boot version
USB boot version
In planning
Remarks
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