Buffer Operation; Figure 10.15 Example Of Synchronous Operation; Figure 10.16 Compare Match Buffer Operation; Table 10.17 Register Combinations In Buffer Operation - Hitachi H8S/2215 Series Hardware Manual

TCNT0 to TCNT2 values
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
H'0000
TIOCA_0
TIOCA_1
TIOCA_2
10.5.3

Buffer Operation

Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers. Buffer operation differs depending on whether TGR has been designated as an input
capture register or as a compare match register. Table 10.17 shows the register combinations used
in buffer operation.

Table 10.17 Register Combinations in Buffer Operation

Channel
0
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register. This operation is illustrated in figure 10.16.
Buffer register
Synchronous clearing by TGRB_0 compare match

Figure 10.15 Example of Synchronous Operation

Timer General Register
TGRA_0
TGRB_0
Compare match signal
Timer general
register

Figure 10.16 Compare Match Buffer Operation

Buffer Register
TGRC_0
TGRD_0
Comparator TCNT
Rev. 3.0, 10/02, page 299 of 686
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