Usb Dmac Transfer Request Register (Udmar) - Hitachi H8S/2215 Series Hardware Manual

15.3.3

USB DMAC Transfer Request Register (UDMAR)

UDMAR is set when data transfer by means of on-chip DMAC is performed for data registers
UEDR2i, UEDR2o, UEDR4i, and UEDR4o corresponding to EP2i, EP2o, EP4i, and EP4o used
for Bulk transfer, respectively. DMAC transfer request sources specified in UDMAR must be two
or less. If two DMAC transfer request sources are specified, a source must use DREQ0 and
another source must use DREQ1. If three or more DMAC transfer requests are specified or if
DREQ0 and DREQ1 usage overlaps, the USB cannot operate correctly. For details on DMAC
transfer, refer to section 15.6, DMA Transfer Specifications.
Bit Bit Name Initial Value R/W
7 EP4oT1 0
6 EP4oT0 0
5 EP4iT1 0
4 EP4iT0 0
3 EP2oT1 0
2 EP2oT0 0
1 EP2iT1 0
0 EP2iT0 0
Description
R/W EP4o DMAC Transfer Request Selection 1, 0
R/W 00: Does not request EP4o DMAC transfer
01: Reserved
10: Requests EP4o DMAC transfer by DREQ0
11: Requests EP4o DMAC transfer by DREQ1
R/W EP4i DMAC Transfer Request Selection 1, 0
R/W 00: Does not request EP4i DMAC transfer
01: Reserved
10: Requests EP4i DMAC transfer by DREQ0
11: Requests EP4i DMAC transfer by DREQ1
R/W EP2o DMAC Transfer Request Selection 1, 0
R/W 00: Does not request EP2o DMAC transfer
01: Reserved
10: Requests EP2o DMAC transfer by DREQ0
11: Requests EP2o DMAC transfer by DREQ1
R/W EP2i DMAC Transfer Request Selection 1, 0
R/W 00: Does not request EP2i DMAC transfer
01: Reserved
10: Requests EP2i DMAC transfer by DREQ0
11: Requests EP2i DMAC transfer by DREQ1
Rev. 3.0, 10/02, page 449 of 686