Hitachi H8S/2215 Series Hardware Manual page 47

Figure 10.14 Example of Synchronous Operation Setting Procedure......................................... 298
Figure 10.15 Example of Synchronous Operation...................................................................... 299
Figure 10.16 Compare Match Buffer Operation ......................................................................... 299
Figure 10.17 Input Capture Buffer Operation............................................................................. 300
Figure 10.18 Example of Buffer Operation Setting Procedure................................................... 300
Figure 10.19 Example of Buffer Operation (1)........................................................................... 301
Figure 10.20 Example of Buffer Operation (2)........................................................................... 301
Figure 10.21 Example of PWM Mode Setting Procedure .......................................................... 303
Figure 10.22 Example of PWM Mode Operation (1) ................................................................. 303
Figure 10.23 Example of PWM Mode Operation (2) ................................................................. 304
Figure 10.24 Example of PWM Mode Operation (3) ................................................................. 305
Figure 10.25 Example of Phase Counting Mode Setting Procedure........................................... 306
Figure 10.26 Example of Phase Counting Mode 1 Operation .................................................... 307
Figure 10.27 Example of Phase Counting Mode 2 Operation .................................................... 308
Figure 10.28 Example of Phase Counting Mode 3 Operation .................................................... 309
Figure 10.29 Example of Phase Counting Mode 4 Operation .................................................... 310
Figure 10.30 Count Timing in Internal Clock Operation............................................................ 313
Figure 10.31 Count Timing in External Clock Operation........................................................... 313
Figure 10.32 Output Compare Output Timing............................................................................ 314
Figure 10.33 Input Capture Input Signal Timing........................................................................ 314
Figure 10.34 Counter Clear Timing (Compare Match)............................................................... 315
Figure 10.35 Counter Clear Timing (Input Capture) .................................................................. 315
Figure 10.36 Buffer Operation Timing (Compare Match).......................................................... 315
Figure 10.37 Buffer Operation Timing (Input Capture) ............................................................. 316
Figure 10.38 TGI Interrupt Timing (Compare Match) ............................................................... 316
Figure 10.39 TGI Interrupt Timing (Input Capture) ................................................................... 317
Figure 10.40 TCIV Interrupt Setting Timing.............................................................................. 317
Figure 10.41 TCIU Interrupt Setting Timing.............................................................................. 318
Figure 10.42 Timing for Status Flag Clearing by CPU............................................................... 318
Figure 10.43 Timing for Status Flag Clearing by DTC or DMAC Activation ........................... 319
Figure 10.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode ................ 320
Figure 10.45 Contention between TCNT Write and Clear Operations....................................... 321
Figure 10.46 Contention between TCNT Write and Increment Operations ............................... 321
Figure 10.47 Contention between TGR Write and Compare Match........................................... 322
Figure 10.48 Contention between Buffer Register Write and Compare Match .......................... 322
Figure 10.49 Contention between TGR Read and Input Capture ............................................... 323
Figure 10.50 Contention between TGR Write and Input Capture .............................................. 323
Figure 10.51 Contention between Buffer Register Write and Input Capture.............................. 324
Figure 10.52 Contention between Overflow and Counter Clearing............................................ 324
Figure 10.53 Contention between TCNT Write and Overflow................................................... 325
Section 11 8-Bit Timers (TMR)
Figure 11.1 Block Diagram of 8-Bit Timer ................................................................................ 328
Rev. 3.0, 10/02, page xlvii of lviii