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cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Start transmission
Read TDRE flag in SSR
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
All data transmitted?
Read TEND flag in SSR
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
Figure 13.14 Sample Multiprocessor Serial Transmission Flowchart
Initialization
TDRE = 1
Yes
Yes
TEND = 1
Yes
Break output?
Yes
<End>
[1] SCI initialization:
[1]
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a
frame of 1s is output, and
[2]
transmission is enabled.
No
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
No
flag to confirm that writing is
[3]
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC is activated by a transmit
data empty interrupt (TXI)
request, and data is written to
No
TDR.
[4] Break output at the end of serial
transmission:
No
To output a break in serial
[4]
transmission, set the port DDR to
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Rev. 3.0, 10/02, page 393 of 686
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