External Bus Release Usage Note; Resets And The Bus Controller - Hitachi H8S/2215 Series Hardware Manual

DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
DMAC: The DMAC sends the bus arbiter a request for the bus when an activation request is
generated.
In the case of a USB request in short address mode or normal mode, and in cycle steal mode, the
DMAC releases the bus after a single transfer.
In block transfer mode, it releases the bus after transfer of one block, and in burst mode, after
completion of the transfer.
6.10.3

External Bus Release Usage Note

External bus release can be performed on completion of an external bus cycle. The CS signal
remains low until the end of the external bus cycle. Therefore, when external bus release is
performed, the CS signal may change from the low level to the high-impedance state.
6.11

Resets and the Bus Controller

In a power-on reset, this LSI, including the bus controller, enters the reset state at that point, and an
executing bus cycle is discontinued.
In a manual reset, the bus controller's registers and internal state are maintained, and an executing
external bus cycle is completed. In this case, WAIT input is ignored and write data is not
guaranteed.
Rev. 3.0, 10/02, page 139 of 686