Figure 7.19 Example Of Full Address Mode (Block Transfer Mode) Transfer - Hitachi H8S/2215 Series Hardware Manual

If a request from another higher-priority channel is generated after burst transfer starts, that
channel has to wait until the burst transfer ends.
If an NMI is generated while a channel designated for burst transfer is in the transfer enabled state,
the DTME bit is cleared and the channel is placed in the transfer disabled state. If burst transfer
has already been activated inside the DMAC, the bus is released on completion of a one-byte or
one-word transfer within the burst transfer, and burst transfer is suspended. If the last transfer
cycle of the burst transfer has already been activated inside the DMAC, execution continues to the
end of the transfer even if the DTME bit is cleared.
Full Address Mode (Block Transfer Mode): Figure 7.19 shows a transfer example in which
TEND output is enabled and word-size full address mode transfer (block transfer mode) is
performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
DMA
read
φ
Address bus
*
Bus release

Figure 7.19 Example of Full Address Mode (Block Transfer Mode) Transfer

A one-block transfer is performed for one transfer request, and after the transfer the bus is
released. While the bus is released, one or more bus cycles are inserted by the CPU or DTC.
In the transfer end cycle of each block (the cycle in which the transfer counter reaches 0), a one-
state DMA dead cycle is inserted after the DMA write cycle.
One block is transmitted without interruption. NMI generation does not affect block transfer
operation.
Note: * TEND output cannot be used with this LSI.
Rev. 3.0, 10/02, page 184 of 686
DMA DMA DMA DMA
write read write dead
Block transfer
DMA DMA DMA
read write read
Bus release Last block transfer
DMA DMA
write dead
Bus release