Hitachi H8S/2215 Series Hardware Manual page 506

Bit Bit Name Initial Value R/W
0 UDCRST 1
Rev. 3.0, 10/02, page 448 of 686
Description
R/W UDC Core Software Reset
Controls reset of the UDC core in the USB module.
When the UDCRST bit is set to 1, the UDC core is
reset and USB bus synchronization operation stops.
At initialization, UDCRST must be cleared to 0 after
D+ pull-up following UIFRST clearing to 0. In the
suspend state, to maintain the internal state of the
UDC core, enter software standby mode after setting
USB module stop mode with the UDCRST bit to be
maintained. After VBUS disconnection detection,
UDCRST must be set to 1.
0: Sets the UDC core in the USB module to operating
state (at initialization, UDCRST must be cleared after
D+ pull-up following UIFRST clearing to 0).
1: Sets the UDC core in the USB module to reset state
(in the suspend state, UDCRST must not be set to 1;
after VBUS disconnection detection, UDCRST must
be set to 1).