Section 8 Data Transfer Controller (Dtc); Features - Hitachi H8S/2215 Series Hardware Manual

Section 8 Data Transfer Controller (DTC)

This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data. Figure 8.1 shows a block diagram of the DTC. The DTC's register
information is stored in the on-chip RAM. When the DTC is used, the RAME bit in SYSCR must
be set to 1. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state
reading and writing of the DTC register information.
8.1

Features

• Transfer possible over any number of channels
 Transfer information is stored in memory
 One activation source can trigger a number of data transfer (chain transfer)
• Three transfer modes
 Normal, repeat, and block transfer modes available
• One activation source can trigger a number of data transfers (chain transfer)
• Direct specification of 16-Mbyte address space possible
• Activation by software is possible
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Module stop mode can be set
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