Clock; Sci Initialization (Asynchronous Mode); Figure 13.7 Relationship Between Output Clock And Transfer Data Phase; (Asynchronous Mode) - Hitachi H8S/2215 Series Hardware Manual

13.4.3

Clock

Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI's serial clock, according to the setting of the C/A bit in
SMR and the CKE0 and CKE1 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used. When an external clock is selected, the basic
clock of average transfer rate can be selected according to the ACS2 to ACS0 bit setting of
SEMR0.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin by
setting CKE1 =0 and CKE0=1. The frequency of the clock output in this case is equal to the bit
rate, and the phase is such that the rising edge of the clock is in the middle of the transmit data, as
shown in figure 13.7.
SCK
0
TxD

Figure 13.7 Relationship between Output Clock and Transfer Data Phase

13.4.4

SCI Initialization (Asynchronous Mode)

Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 13.8. When the operating mode, or
transfer format, is changed for example, the TE and RE bits must be cleared to 0 before making the
change using the following procedure. When the TE bit is cleared to 0, the TDRE flag is set to 1.
Note that clearing the RE bit to 0 does not initialize the contents of the RDRF, PER, FER, and
ORER flags, or the contents of RDR. When the external clock is used in asynchronous mode, the
clock must be supplied even during initialization.
Rev. 3.0, 10/02, page 384 of 686
D0 D1 D2 D3

(Asynchronous Mode)

D4 D5 D6 D7
1 frame
1 1
0/1