Usb Endpoint Stall Register 0 (Uestl0) - Hitachi H8S/2215 Series Hardware Manual

15.3.9

USB Endpoint Stall Register 0 (UESTL0)

UESTL0 is used to forcibly stall the endpoints for EP0 to EP3. While the bit is set to 1, the
corresponding endpoint returns a stall handshake to the host. However, note that EP3 (Isochronous
transfer) does not return a stall handshake.
The stall bit for endpoint 0 (EP0STL) is cleared automatically on reception of 8-bit command data
for which decoding is performed by the function. When the SetupTS flag in UIFR0 is set, a write
of 1 to the EP0STL bit is ignored. For details, refer to section 15.5.11, Stall Operations.
Bit Bit Name Initial Value R/W
7 EP3oSTL 0
6 EP3iSTL 0
5 EP2oSTL 0
4 EP2iSTL 0
3 EP1iSTL 0
2 — 0
1 — 0
0 EP0STL 0
Description
R/W EP3o stall
0: Cancels the EP3o stall state.
1: Places the EP3o stall state.
R/W EP3i stall
0: Cancels the EP3i stall state.
1: Places the EP3i stall state.
When the EP3i is placed in the stall state, a 0-length
packet is returned for the first IN token. For the
following IN token, nothing is returned.
R/W EP2o stall
0: Cancels the EP2o stall state.
1: Places the EP2o stall state.
R/W EP2i stall
0: Cancels the EP2i stall state.
1: Places the EP2i stall state.
R/W EP1i stall
0: Cancels the EP1i stall state.
1: Places the EP1i stall state.
R Reserved
R These bits are always read as 0 and cannot be
modified.
R/W EP0 stall
0: Cancels the EP0 stall state.
1: Places the EP0 stall state.
Rev. 3.0, 10/02, page 455 of 686